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  • Responsibilities:

    1. Build verification platforms, write verification automation scripts, speed up the verification process and enhance the automation of verification;
    2. Develop, oversee and execute chip verification plans and participate in system-level verification, module-level verification and post-simulation of chips;
    3. Solve the problems related to tools and environment during chip verification.

    Qualifications:

    1. Proficient in Linux/Unix environment, Perl/Python, C/C++ and Unix Shell;
    2. Proficient in Verilog and System Verilog languages as well as mainstream EDA simulation tools such as VCS and Verdi;
    3. Proficient in chip verification process and UVM verification methodology, and be able to build verification platforms using UVM + SystemVerilog;
    4. Strong technical writing skills;
    5. 3 years or above experience as a design or verification engineer, and has participated in at least one ASIC/SOC tape-out project;
    6. Those with the following skills are preferred;
    7. Familiar with Ethernet physical layer protocol and serdes physical layer protocol.

  • Responsibilities:

    1. Define and develop DFT strategies, methodologies, and architectures, including clock/reset management and scan channel partitioning for each design tile.
    2. Design and implement DFT features such as scan insertion, observation chain controller (OCC) insertion, Enhanced Deterministic Test (EDT) IP generation, and automatic test pattern generation (ATPG) using Mentor Graphics tools.
    3. Create and verify test structures, debug structures, and comprehensive test plans.
    4. Oversee and contribute to the generation of ATPG and MBIST (Memory BIST) test vectors, ensuring pre- and post-silicon simulation and validation.
    5. Insert, verify, and deliver tile- and top-level DFT netlists, including scan chain integration for analog IPs, BSCAN insertion, MBIST insertion, test point insertion, and scan timing constraint (SDC) management.
    6. Validate DFT coverage goals and verify that post-physical design (post-PD) implementations meet DFT specifications.

    Qualifications:

    1. Bachelor’s degree or above in Electronics, Communications, Computer Engineering, or related fields.
    2. Strong understanding of digital logic design, IP and SoC design, and DFT architectures.
    3. Proficient in DFT methodologies and structural debug techniques including JTAG, IEEE 1500, MBIST, scan dump, and memory dump.
    4. Experience with logic synthesis, simulation, and verification.
    5. Give feedback on general, formal inspection and DFT work problems to IP development and SoC to assist in optimization.
    6. Proficiency in programming/scripting languages such as Python, C/C++, Shell scripting, TCL, and Makefiles.
    7. Strong analytical and problem-solving skills with excellent organizational, written, and verbal communication abilities.
    8. Fluent in English.

  • Responsibilities:

    1. Lead front-end SoC chip design, including IP evaluation and selection, IP integration, bus design, and clock planning.
    2. Participate in defining architecture and microarchitecture features of SoC blocks.
    3. Apply various design strategies and tools to optimize RTL for power, performance, area, and timing goals, ensuring design integrity for physical implementation.
    4. Support the verification team by reviewing verification plans, locating and solving design issues, and ensuring correct verification of design features.
    5. Assist in FPGA platform testing and support system-level hardware and software co-debugging.
    6. Perform quality checks across RTL design aspects, including timing and power convergence.
    7. Work with IP providers to integrate and validate IPs at the SoC level, ensuring smooth IP-to-SoC handoff.

    Qualifications:

    1. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, Communications, Mathematics, or a related field.
    2. Strong proficiency in Verilog for logic design and development; familiar with digital circuit debugging techniques and SoC chip design processes.
    3. Hands-on experience with industry-standard design tools such as VCS, Spyglass, Design Compiler (DC), and related EDA tools.
    4. Solid understanding of computer architecture; experience with ARM or RISC-V system architectures is preferred.
    5. Familiarity with AMBA bus protocols; experience with NoC/NiC development and integration is a plus.
    6. Knowledge of memory technologies such as DDR, NOR Flash, and NAND Flash, with experience in their development and integration preferred.
    7. Understanding of interface protocols including Ethernet, PCIe, USB, SPI, UART, and I2C; hands-on experience with integration preferred.

  • Responsibilities:

    1. Participate in the design and architecture of high-speed (GHz) CMOS interface chips, including SPEC definition and overall chip planning.
    2. Design, simulate, and optimize high-performance analog and mixed-signal circuits, with a focus on modules such as PLLs, CDRs, high-speed drivers, linear EQs, DFEs, multiplexers, and demultiplexers.
    3. Research and implement optimal circuit architectures for high-speed and high-performance applications.
    4. Responsible for the design of modules including (but not limited to) PLL, CDR, high-speed Driver, linear EQ, DFE, Mux and DeMux, etc.
    5. Participate in the simulation and verification of Analog Top circuits, and perform full-chip simulation and verification with digital circuit design engineers.
    6. Collaborate with layout engineers to guide layout design and optimize performance based on post-layout simulation results.
    7. Create behavioral models to support verification simulations and ensure design meets electrical, timing, and pre-silicon verification requirements.
    8. Support product engineers in quality qualification assessments, yield maintenance, and failure analysis of chip products.

    Qualifications:

    1. Strong knowledge of analog circuit design in deep submicron CMOS processes, with experience in basic modules such as LDOs, bandgaps, opamps, comparators, current bias circuits, and oscillators.
    2. Familiar with common SerDes protocols like PCIe, HDMI, USB, eDP, MIPI, DDR, and experienced in designing modules such as linear EQ, CDR, and drivers.
    3. In-depth understanding of the IC design and development process, and proficient in using standard EDA development tools.
    4. Proven track record with multiple successful tape-outs and complete product development experience.
    5. Skilled in using test instruments such as oscilloscopes, spectrum analyzers, and network analyzers.
    6. Knowledge of Verilog-A and Verilog is a plus.
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